Fall 2012 – Summer 2013
Electrical Engineering : Trends in technology. CISC vs. RISC architectures. Pipelining. Instruction level parallelism. Data and Control Hazards. Static prediction. Exceptions. Dependencies. Loop level paralleism. Dynamic scheduling, branch prediction. Branch target buffers. Superscalar and N-issue machines. VLIW. ILP techniques. Cache analysis and design. Interleaved and virtual memory. TLB translations and caches.
Terms: Winter 2013
Instructors: Warren Gross (Winter)